Dac_fsm is implemented as a state machine.įigure 5: Control Structure dac_fsm State MachineĪfter the convert signal has been recognized, the bit_count counter is loaded with the value 15. In order to adhere to the values of t4, t5 and t6 given in Figure 1, dac_fsm works on the falling edge of CLK_30. The module dac_fsm controls the generation of the control / data signals to the DAC. Module dac_fsm for two clock implementation The block diagram of sync_stage is shown in Figure 4. Corresponding signals from the dac_fsm are transmitted from the CLK_30 domain to the CLK_120. The sync_stage module transports the convert signal from the CLK_120 domain to the CLK_30 domain. The control unit dac_fsm is part of the CLK_30 domain. The dac_sample_gen module works with CLK_120. The mode_select control signal controls the generation of either a square-wave signal or a triangular-shaped signal as input data for the DAC. The block diagram of dac_sample_gen is shown in Figure 3. The sample rate is set via sample_select signals and is given in Table 1. The sample signal initiates the transmission of the digital data to the DAC. The module dac_sample_gen generates the sample signal (convert) for the dac_fsm. The PLL generates two internal, phase-synchronous clocks, CLK_120 and CLK_30, from the external clock CLK (100 MHz). Internal Clock CLK_120 Frequency: 120 MHZ Implementation of the two clock domain solution is shown in Figure 2.įigure 2: Two Clock Domain SPI Interface Implementation The timing parameters t4, t5 and t6 are given special attention in the specification of timing constraints and will be used in the set_output_delay constraints.įigure 1: Timing Diagram and Timing Characteristics In this example, the SCLK frequency is 30 MHz. Figure 1 shows the timing diagram of the interface and the timing parameters. The AD7303 module from Analog Devices was used as the external DAC. In both cases, two fundamentally different approaches to implementing the interface are presented. The second blog will describe the implementation of a SPI interface to an ADC (the ADC AD7476 from Analog Devices) using a single clock domain. This first blog describes the implementation of an SPI interface to a DAC (an AD7303 DAC from Analog Devices) using two clock domains. This blog (the first in a two part series) describes the implementation of interfaces to SPI-based external components using CrossLink-NX FPGAs. Lattice CrossLink™-NX FPGAs have a rich feature set to accelerate the implementation of high and low speed interfaces. The posts are authored by FPGA design experts from the Lattice Education Competence Center (LEC2), the official global provider of training services focused exclusively on Lattice’s award-winning low power FPGAs and solution stacks. “The LEC2 Workbench” is an ongoing series of technical blog posts focused on application development using Lattice products.
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